Product | Details | Total |
---|---|---|
![]() | Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops Rs4,500.00 A new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits… | Rs4,500.00 |
![]() | Web based hospital network management system Previous price: Save Rs1,000.00 | Rs5,500.00 |
![]() | A Short-Channel-Effect-Degraded Noise Margin Model for Junctionless Double-Gate MOSFET Working on Subthreshold CMOS Logic Gates Rs4,500.00 Based on the device and equivalent transistor model, we present a short-channel-effect (SCE)-degraded noise… | Rs4,500.00 |
Cart totals
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SubtotalRs14,500.00
9% CGSTRs1,305.00
9% SGSTRs1,305.00
Total
Rs17,110.00