MIMO-OFDM is the foundation for most advanced wireless local area network (Wireless LAN) and mobile broadband network standards. The efficient architecture of 4*4 64-QAM MIMO detectors are mainly used for the wireless communication. The system proposes a hard-output error-resilient K-Best MIMO detector architecture possessing. In this architecture, we implement hierarchical tree arrangement based MIMO 64-QAM detector architecture. This architecture to modify the IPM processor and the PCM blocks in MIMO detector architecture. This optimization technique to reduce the power consumption and increase the speed also. An area-efficient symbol detector is proposed for multiple-input multiple-output (MIMO) communication systems with reduced buffer memory architecture. The efficient high-throughput VLSI implementation of Soft-output MIMO detectors for high-order constellations and large antenna configurations has been a major challenge in the literature. This thesis introduces a novel Soft-output K-Best scheme that improves BER performance and reduces the computational complexity significantly by using three major improvement ideas. It also presents an area and power efficient VLSI implementation of a 4×4 64-QAM Soft K-Best MIMO detector that attains the highest detection throughput of 2 Gbps and second lowest energy/bit reported in the literature, fulfilling the aggressive requirements of emerging 4G standards such as IEEE 802.16m and LTE Advanced. A low-complexity and highly parallel algorithm for QR Decomposition, an essential channel pre-processing task, is also developed that uses 2D, Householder 3D and 4D Givens Rotations. Test results for the QRD chip, fabricated in 0.13μm CMOS, show that it attains the lowest reported latency of 144ns and highest QR Processing Efficiency. This paper presents a hardware-efficient architecture for 4×4 and 8×8 high-throughput MIMO detectors. The adopted non-constant K-best algorithm tends to keep more survival nodes in top search tree layers and reduce computational complexity in bottom layers as opposed to the conventional K-best algorithm. A pipelined architecture is used to generate one detection output per clock cycle, thus meeting multi-gigabit throughput requirements for advanced wireless communication systems. This paper also presents a discussion on the scalability of this architecture with respect to the setting of QAM size, K values, and antenna number.