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Achieving High-Performance On-Chip Networks With Shared-Buffer Routers

Product Code:PROJ3408
Availability:In Stock
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  • 3,000.00INR

Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing communi­cation requirements in digital systems. Network-on-chip (NoC) has emerged as a vital factor that determines the performance and power consumption of many core systems. A novel switching mechanism, called virtual circuit switching, is implemented with circuit switching and packet switching. Our work, to modify the router architecture design using the memory based selection arrangement and to design the overall NOC architecture. For obtaining low latency and low power we use hybrid scheme for NOC. virtual circuit switching mechanism is proposed because it intermingle with circuit switching and packet switching. multiple virtual circuit-switched (VCS) connections are allowed to share a common physical channel. Moreover, a path allocation algorithm is proposed in this paper to determine VCS connections and circuit-switched connections on a mesh-connected NoC, such that both communication latency and power are optimized. A set of synthetic and real traffic workloads are exploited to evaluate the effectiveness of the proposed hybrid scheme. Our proposed hybrid scheme can efficiently reduce the communication latency and power. For instance, for real traffic workloads, an average of 20.3% latency reduction and 33.2% power saving can be obtained when compared with the baseline NoC. Moreover, when compared with the NoC with virtual point-to-point connections (VIP), the proposed hybrid scheme can reduce the latency by 6.8% with the power decreasing by 11.3% averagely.


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Tags: 2014, Matlab, Network Projects

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