FPGA Projects
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
The digital architecture is mainly used in all type of real world application architectures and th..
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
The wire sensor network used to the data transmission process and to optimize the time and increase ..
Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
A fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricula..
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-p..
Low-power technique for dynamic comparators
A low-power technique to reduce the power consumption of the dynamic comparators is presented. Usi..
Low-Power-Clock-Distribution-Using-a-Current-Pulsed-Clocked-Flip-Flop
In this proposed system is based on communication process. This design mainly consists three units. ..
Low-Power-Pulse-Triggered-Flip-Flop-Design-Based-on-a-Signal-Feed-Through-Scheme
Flip-flops and latches are used as data storage elements. Such data storage can be used for storage ..
Low‑power-half‑select-free-single‑ended-10-transistor-SRAM-cell
In this proposed implementation design is based on 11T and 12T SRAM cell for automotive electronics ..
MACS: A Highly Customizable Low-Latency Communication Architecture
Network-on-Chip (NoC) architectures represent a promising design paradigm to cope with increasing ..
Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression
A new compression technique of next-iteration initialization metrics for relaxing the storage dema..
Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM
RRobust organ segmentation is a prerequisitefor computer-aided diagnosis, quantitative imaging ana..
Multiplierless Unity-Gain SDF FFTs
A novel approach to implement multiplierless unity-gain single-delay feedback fast Fourier transfo..
New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements
This paper presents novel designs of static dual-edgetriggered (DET) flip-flops that exhibit uniqu..
Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter
An open-loop fractional divider is proposed to eliminate the deterministic jitter caused by the co..
Optimized Active Single Miller Capacitor Compensation With Inner Half Feed for ward Stage for Very High Load Three Stage OTAs
A new effective single-Miller capacitor compensation topology for three-stage amplifiers with very..