FPGA Projects
CMOS Integrated Time Mode Temperature Sensor for Self Refresh Control in DRAM Memory Cell
The product proposes a CMOS smart temperature sensor for a self-refresh controller in DRAM memory ce..
Compensation Method for Multistage Opamps With High Capacitive Load Using Negative Capacitance
It is shown that negative capacitance (NC) circuits can be systematically used to improve the gain..
Computing Seeds for LFSR-Based Test Generation From Nontest Cubes
It is necessary to ensure the faultless test generation when designing the circuits. For that we h..
Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm
The filter process mainly used to DSP and DIP real world application. The filter process to remove t..
Design and Analysis of a Highly Efficient Linearized CMOS Subharmonic Mixer for Zero and Low-IF Applications
The distortion analysis of a linearized CMOS subharmonic mixer (SHM) based on a Volterra series an..
Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry
Many packaging and structural materials are made of conductive materials such as metal or carbon-f..
Design of an offset-tolerant voltage sense amplifier bit-line sensing circuit for SRAM memories
The design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset c..
Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata
A digital comparator or magnitude comparator is a hardware electronic device that takes two numbers...
Design of QPP Interleavers for the ParallelTurbo Decoding Architecture
Parallel interleaver is an indispensable component for the parallel turbo decoder. The ever increa..
Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
Approximate computing has received significant attention as a promising strategy to decrease power..
Dual-Band Waveform Generator With Ultra-Wide Low-Frequency Tuning-Range
A novel mixed-signal low-power dual-band square/triangular waveform generator (WFG) chip with a wi..
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces
Wireless 3-D network-on-chips (NoCs) with inductive-coupling ThruChip interfaces provide a large d..
Efficient Register Renaming and Recovery for High-Performance Processors
An efficient hardware solution to perform table lookup is the content addressable memory (CAM). A CA..
Energy and Area Efficient Three-Input XOR/ XNORs With Systematic Cell Design Methodology
The influence of electronics in pervasive computing needs confidentiality of the electronically proc..
Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories
Error correction code (ECC) and built-in selfrepair (BISR) techniques by using redundancies have b..