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Hard-Information Bit-Reliability Based Decoding Algorithm for Majority-Logic Decodable Nonbinary LDPC Codes

Product Code:PROJ7260
Availability:In Stock
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  • 4,500.00INR

A modified bit-reliability based decoding algorithm is presented based on a recent work by Huang et al. For the presented algorithm, only one Galois field element is passed and exchanged along the edges of the Tanner graph. At variable nodes, full messages rather than extrinsic messages are processed to further reduce the computational complexity. At check nodes, only hard reliability is considered and the main operation is to compute the check-sum and send one extrinsic symbol back to variable nodes.

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Tags: VLSI-Verilog-VHDL-Xillinx-CMOS-TannerTool-FPGA

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