Hi there! Click one of our representatives below and we will get back to you as soon as possible.

CMOS Projects

star_border star_border star_border star_border star_border

1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS

Nowadays the research works going on the pipelined ADC for power reduction and predictive error rate..

3,000.00INR
star_border star_border star_border star_border star_border

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

A 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity,..

4,500.00INR
star_border star_border star_border star_border star_border

A 40–170 MHz PLL-Based PWM Driver Using2-/3-/5-Level Class-D PA in 130 nm CMOS

A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplif..

4,500.00INR
star_border star_border star_border star_border star_border

A Colpitts CMOS Quadrature VCO Using Direct Connection of Substrates for Coupling

To improve the phase noise, various experiments are done to modify the coupling networks. The coupli..

3,000.00INR
star_border star_border star_border star_border star_border

A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing

Integral histogram image can accelerate the computing process of feature algorithm in computer vis..

4,500.00INR
star_border star_border star_border star_border star_border

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

 Transpose form finite-impulse response (FIR) filters are inherently pipelined and support mu..

4,500.00INR
star_border star_border star_border star_border star_border

A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic

A high-throughput energyefficient Successive Cancellation (SC) decoder architecture for polar code..

4,500.00INR
star_border star_border star_border star_border star_border

A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones

 Conventional active noise cancelling (ANC) headphones often perform well in reducing the low..

4,500.00INR
star_border star_border star_border star_border star_border

A Low-Power Robust Easily CascadedPentaMTJ-Based Combinational and Sequential Circuits

Memory system is the heart of the processor. On-chip memory occupies a more portion of the over-all..

4,500.00INR
star_border star_border star_border star_border star_border

A New XOR-Free Approach for Implementation of Convolutional Encoder

XOR Free Encoder means error correcting codes. This work is to implement the partial parallel enco..

4,500.00INR
star_border star_border star_border star_border star_border

A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO

Nowadays, many applications require simultaneous computation of multiple independent fast Fourier ..

4,500.00INR
star_border star_border star_border star_border star_border

A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell

                 &nb..

4,500.00INR
star_border star_border star_border star_border star_border

Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes

This pre-processing allows for employing a tree-based search algorithm at the second stage that fin..

4,500.00INR
star_border star_border star_border star_border star_border

An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors

 Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) ..

4,500.00INR
star_border star_border star_border star_border star_border

An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code

Channel coding is commonly incorporated to obtain sufficient reception quality in wireless mobile c..

4,500.00INR
Showing 1 to 15 of 36 (3 Pages)
LiveZilla Live Chat Software
Free Website Hit Counter
Free website hit counter