Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block
The system proposes an adopting algorithmic noise tolerant (ANT) architecture with the fixed-width multiplier for a reliable low-power multiplier design to build the reduced precision replica redundancy block (RPR), in this paper. The ANT technique includes both main digital signal processor (MDSP) and error correction (EC) block the proposed algorithmic noise tolerant (ANT) architecture can meet the demand of high precision, low power consumption, and area efficiency. Using the fixed-width RPR, the computation error can be corrected with lower power consumption and lower area overhead. The system takes use of probability, statistics, and partial product weight analysis to find the approximate compensation vector for a more precise RPR design. The proposed fixed-width RPR multiplier not only performs with higher SNR but also with lower circuitry area and lower power consumption. In order not to increase the critical path delay, the system restricts the compensation circuit in RPR must not be located in the critical path. As a result, the system can realize the ANT design with smaller circuit area, lower power consumption, and lower critical supply voltage.
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