VLSI Projects
Low-Complexity Low-LatencyArchitecture for Matching of Data Encoded With Hard Systematic Error-Correcting Code
We renovate the SA-based direct compare architecture to reduce the latency and hardware complexity b..
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme
A digital-to-analog converter (DAC) is a function that converts digital data into an analog signal. ..
A 65 nm Cryptographic Processor for High Speed Pairing Computation
Cryptographic processors are becoming the standard way to enforce data-usage policies. The designers..
A Multichannel Oscillator for a Resonant Chemical Sensor System
Sensors (detectors/transducers) covers a wide category of devices used to monitor, measure, test, an..
A Power-Efficient Continuous-Time Incremental Sigma-Delta ADC for Neural Recording Systems
An analog-to-digital converter is a device that converts a continuous physical quantity to a digital..
Achieving Memory Access Equalization via Round-trip Routing Latency Prediction in 3D Many-core NoCs
Abstract: Three dimensional Networks-on-Chip (3D NoCs) have attracted a growing interest..
Algorithm and Architecture for a Low-Power Content Addressable Memory Based on Sparse Clustered Networks
Content-addressable memory (CAM) is a special type of computer memory used in certain very-high-spee..
An 8T Low Voltage and Low Leakage Half Selection Disturb Free SRAM Using Bulk CMOS and FinFETs
Flip-flops and latches are used as data storage elements. Such data storage can be used for storage ..
Analysis of Leakage Current and Leakage Power Reduction during Write operation in CMOS SRAM Cell
ABSTRACT Flip-flops and latches are used as data storage elements. Such data storag..
Drowsy Driver Detection using Representation Learning
Driver fatigue is a significant factor in a large number of vehicle accidents. Thus, driver drowsine..
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
VLSI technology is to optimize the any type of digital architecture. Because this type of optimizati..
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule
This project proposes Dynamic multi frame processing schedule. This schedule efficiently utilizes th..
Low-Power Programmable PRPG With Test Compression Capabilities
BIST (Build-in Self-Test), schemes are the solution of testing VLSI devices. BIST is used to make fa..
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block
The system proposes an adopting algorithmic noise tolerant (ANT) architecture with the fixed-width ..
Resource Shared Crypto Coprocessor of AES Enc Dec With SHA 3
Cryptographic co-processors are integral to the modern System-on-Chips. Flexibility in such designs..