VLSI Projects
0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier
A simple high-performance architecture for bulkdriven operational transconductance amplifiers (OTA..
11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids
Now a days, the communication industry field is mainly focused by high data transfer and more channe..
75 GBd InP-HBT MUX-DAC module for high-symbol-rate optical transmission
An ultra-broadband 6 bit digital-to-analog ue converter (DAC) has been designed and fabricated in ..
A 0.45-V Low-Power OOK/FSK RF Receiver in 0.18 µm CMOS Technology for Implantable Medical Applications
A 0.45-V low-power 0.18 ?m CMOS OOK/FSK RF receiver for implantable medical applications is propos..
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process
A 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity,..
A 16 Kb Spin-Transfer Torque Random Access Memory With Self-Enable Switching and Precharge Sensing Schemes
MRAM is basically used as data storage elements. Such data storage can be used for storage of state...
A 40–170 MHz PLL-Based PWM Driver Using2-/3-/5-Level Class-D PA in 130 nm CMOS
A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplif..
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC
Now days the usage of continuous-time incremental sigma-delta ADC in neural recording system is in..
A CMOS Ultra-wideband Pulse Generator for 3–5 GHz Applications
A low-power ultrawideband (UWB) pulse generator based on pulsed oscillator architecture for 3–5 GHz..
A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode Controlled Switching Regulators
A one-pin mode transition circuit that addresses the issues related to clock synchronization..
A Compact-Area Low-VDDmin 6T SRAM with Improvement in Cell Stability Read Speed and Write Margin Using a Dual-Split-Control-Assist Scheme
Previous 6T SRAMs commonly employ a wordline voltage underdrive (WLUD) scheme to suppress half-sele..
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient
Reconfigurable digital filter is being widely used in applications such as communication and signa..
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
Integral histogram image can accelerate the computing process of feature algorithm in computer vis..
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply
A new power-efficient electrocardiogram acquisition system that uses a fully digital architecture ..
A graph based algorithm to minimize total wire length in vlsi channel routing
The important problem in VLSI layout design is minimization of total wire length. Minimization of wi..