An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code
Channel coding is commonly incorporated to obtain sufficient reception quality in wireless mobile communications transceiver to counter channel degradation due to inter-symbol interference, multipath dispersion, and thermal noise induced by electronic circuit devices. High speed and high throughput hardware for encoder and decoder could be useful in communication field. Due to the channel achieving property, the GOLAY code has become one of the most favorable error-correcting codes. As the GOLAY code achieves the property asymptotically, however, it should be long enough to have a good error-correcting performance. In this project, a new algorithm has been proposed for CRC based encoding scheme, which devoids of any linear feedback shift registers (LFSR). In addition, efficient architectures have been proposed for both Golay encoder and decoder, which outperform the existing architectures in terms of speed and throughput. The proposed architectures were simulated and tested on Virtex-4 platform. Although the CRC encoder and decoder is intuitive and easy to implement, and to reduce the huge hardware complexity required. The proposed method it improve the transmission system performance level. In this architecture, our work is to design a GOLAY code based encoder and decoder architecture using CRC processing technique. This technique is to reduce the circuit complexity for data transmission and reception process.
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