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A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing

Product Code:PROJ7088
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  • 4,500.00INR

Integral histogram image can accelerate the computing process of feature algorithm in computer vision, but exhibits high computation complexity and inefficient memory access. In this paper, we propose a configurable parallel architecture to improve the computing efficiency of integral histogram. Based on the configurable design in the architecture, multiple integral objects for integral histogram image, such as image intensity, image gradient, and local binary pattern, are well supported. Meanwhile, by means of the proposed strip-based memory partitioning mechanism, this architecture processes the integral histogram quickly with maximal parallelism in a pipeline manner.


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Tags: VLSI-Verilog-VHDL-Xillinx-CMOS-TannerTool

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