A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture
A new very large scale integration (VLSI) algorithmic rule for a 2N length discrete hartley transform (DHT) that may be expeditiously enforced on a extremely standard and parallel VLSI design having a regular structure is given. The DHT algorithmic rule may be expeditiously split on many parallel elements that may be dead at the same time. Moreover, the planned algorithmic rule is compatible for the subexpression sharing technique that may be used to significantly reduce the hardware complexness of the highly parallel VLSI implementation. The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the subexpression sharing technique that can be used to significantly reduce the hardware complexity of the highly parallel VLSI implementation. Using the advantages of the proposed algorithm and the fact that we can efficiently share the multipliers with the same constant, the number of the multipliers has been significantly reduced such that the number of multipliers is very small comparing with that of the existing algorithms. Moreover, the multipliers with a constant can be efficiently implemented in VLSI.
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