Description

The main objective of the proposed work is to obtain the low power in the tunable delay gate model. The matching properties of the proposed method is to increase the matching properties of the CMOS. For that delay gate analysis, two different inverter configuration is used. The different configurations are “current starved inverter” (CSI) and “output split inverter” (OSI). The Current Starved Inverter (CSI) is used as a delay element in time measurement circuits. Transmission gate based delay element is fast due to relatively low resistive path between input and output. An alternative output-split inverter (OSI) structure of a delay gate model is proposed. The only topological difference between the CSI and the OSI circuits is the location of the current limiting transistor MD on the drain rather. The effects of parameter variation of MOS transistors in the realizations of the CSI and OSI delay gates are the same circuit realizations as the mismatch Monte Carlo MOS transistor models and bias voltages tuned for both gates to ensure the same mean value of the generated delays . It can be seen that the random variability of the generated delay is larger in the CSI gate. The detailed simulation results accounting for the variability of the generated delay caused by mismatch of individual transistors in the delay gates.