Description

Research into Network On Chip (NOC) is important with increasing the number of cores in Single chip. The classical interconnection of System On Chip (SOC) replaced with the proposed NOC. a new fault-tolerant routing algorithm for Networks on Chip (NoCs) is proposed in this paper. The proposed algorithm is based on a combination between a dynamic routing algorithm and a communication load clustering technique in a 2D mesh topology. Nowadays System-On-Chips (SoCs) have evolved considerably in term of performances, reliability and integration capacity. The last advantage has induced the growth of the number of cores or Intellectual Properties (IPs) in a same chip. Unfortunately, this important number of IPs has caused a new issue which is the intra-communication between the elements of a same chip. To resolve this problem, a new paradigm has been introduced which is the Network – On – Chip (NoC). Since the introduction of the NoC paradigm in the last decade, new methodologies and approaches have been presented by research community and many of them have been adopted by industrials. Our phase work to modify the router connection and to optimize the no of memory element in noc architecture. The global router based design to optimize the router placements in noc design and to control the router data transfer process. To apply the hop position using the clustering based algorithm in NOC router architecture . Then to improve the core system performance level compare to the existing methodology.