Description

This project proposes Dynamic multi frame processing schedule. This schedule efficiently utilizes the layered-LDPC decoding with minimum pipeline stages. And this project presents architecture of block-level-parallel layered decoder for irregular LDPC code. This code can be reconfigured to support various block lengths and code rates in (WiFi) wireless-communication standard. The system presents an efficient comparison techniques for both column and row layered schedule and rejection-based high-speed circuits to compute the two minimum values from multiple inputs required for row layered processing of hardware-friendly min-sum decoding algorithm. This system utilizes three pipeline stages to evaluate this scheme. The system show the result as good speed with lower area as compared to state-of-the-art circuits in this project. The system proposed an efficient-comparison technique to be used in the construction of high-speed circuits for extracting the minimum values with smaller number of pipeline stages. This resulted in lower latency and good frequency scaling. A dynamic multiple-frame processing for LDPC-decoding algorithm is used to remove the pipeline bubbles and minimize the memory overheads. The BER performance analysis of this decoder for various code-rates has been performed in additive-white Gaussian-noise (AWGN) channel environment.