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Low-Complexity Low-LatencyArchitecture for Matching of Data Encoded With Hard Systematic Error-Correcting Code

Product Code:PROJ3190
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We renovate the SA-based direct compare architecture to reduce the latency and hardware complexity by resolving the aforementioned drawbacks. More specifically, we consider the characteristics of systematic codes in designing the proposed architecture and propose a low-complexity processing element that computes the Hamming distance faster. Therefore, the latency and the hardware complexity are decreased considerably even compared with the SA based architecture. An encoder is a device, that converts information from one format or code to another, for the purposes of standardization, speed, secrecy, security or compressions. Hamming is also known for developing the concept of a distance. The distance is defined as the minimum number of bits that would have to flip in order to go from one codeword to another. All error correcting mechanisms correct to the nearest codeword to the received string. Therefore the maximum number of errors a code can reliably fix is less than half of the distance between the closest two code words. To optimize the hardware complexity using BWA architecture. In this architecture, proposed modified T-algorithm used to efficient computation of the Hamming distance. And optimize the error fault analysis method, to reduce the hardware complexity. The proposed architecture examines whether the incoming data matches the stored data if a certain number of erroneous bits are corrected. Hamming code is one of such forward error correcting code which has got many applications. In this paper the algorithm for hamming code is discussed and then implementation of it in verilog is done to get the results. Hamming code is an upgrading over parity check method. Here a code is implemented in verilog in which 4-bit of information data is transmitted with 3-redundancy bits. A new architecture for matching the data protected with an error-correcting code (ECC) is presented in this brief to reduce latency and complexity. Based on the fact that the code word of an ECC is usually represented in a systematic form consisting of the raw data and the parity information generated by encoding, the proposed architecture parallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the efficient computation of the Hamming distance. Grounded on the BWA, the proposed architecture examines whether the incoming data matches the stored data if a certain number of erroneous bits are corrected. For a (40, 33) code, the proposed architecture reduces the latency and the hardware complexity by ∼32% and 9%, respectively, compared with the most recent implementation.


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Tags: 2015, VLSI, Communication

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