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Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

Starting at: Rs.5,500.00

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 Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops

 A new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, singleoutput, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge.


 


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  • Model: PROJ7363
  • 999 Units in Stock
  • Manufactured by: ClickMyProjects

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This product was added to our catalog on Saturday 24 June, 2017.

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