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Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

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 Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design

 As the circuit complexity increases, the number of internal nodes increases proportionally, and individual internal nodes are less accessible due to the limited number of available I/O pins. To address the problem, we proposed power line communications (PLCs) at the IC level, specifically the dual use of power pins and power distribution networks for application/ observation of test data as well as delivery of power. A PLC receiver presented in this paper intends to demonstrate the proof of concept, specifically the transmission of data through power lines.


 


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  • Model: PROJ7325
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This product was added to our catalog on Thursday 22 June, 2017.

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