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Design of an offset-tolerant voltage sense amplifier bit-line sensing circuit for SRAM memories

Design of an offset-tolerant voltage sense amplifier bit-line sensing circuit for SRAM memories

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 Design of an offset-tolerant voltage sense amplifier bit-line sensing circuit for SRAM memories

 The design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset cancellation and compensation solutions. FCMOS inverters, brought to operate in their maximum gain region, are used to compensate the systematic offset of the sense amplifier and reduce the sensing delay. Systematic offset of the inverter amplifiers is cancelled by means of equalising feedback connections.


 


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  • Model: PROJ7428
  • 999 Units in Stock
  • Manufactured by: ClickMyProjects

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This product was added to our catalog on Tuesday 11 July, 2017.

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