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Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

Starting at: Rs.5,500.00

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 Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier

proposes the design of a low-voltage static random access memory (SRAM) for biomedical chip applications. The SRAM is designed using a standard 8T bit cell, featuring a shared data-aware write scheme and a differential reference-based sense amplifier. The proposed techniques make it possible for the 8T SRAM to use bit-interleaving architecture and address the half-select problem, achieving area efficiency and power reduc-tion. A 96-kb 8T SRAM test chip is implemented in a 65-nm CMOS process to verify the proposed schemes, which operates functionality at a VDD minof 0.36 V and has a power consumption of 5.1 ?W


 


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  • Model: PROJ7498
  • 999 Units in Stock
  • Manufactured by: ClickMyProjects

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This product was added to our catalog on Friday 28 July, 2017.

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