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Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks

Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks

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Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks

 A low-power content-addressable memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data. The proposed architecture is based on a recently developed sparse clustered network using binary connections that On -average eliminates most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared with that of a conventional low-power CAM design. Given an input tag, the proposed architecture computes a few possibilities for the location of the matched tag and performs the comparisons on them to locate a single valid match. TSMC 65-nm CMOS technology was used for simulation purposes. Following a selection of design parameters, such as the number of CAM entries, the energy consumption and the search delay of the proposed design are 8%, and 26% of that of the conventional NAND architecture, respectively, with a 10% area overhead. A design methodology based on the silicon area and power budgets, and performance requirements is discussed.


 


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  • Model: PROJ5040
  • 999 Units in Stock
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This product was added to our catalog on Wednesday 07 September, 2016.

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