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A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

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A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT

 We present an ef?cient combined single-path delay commutator-feedback (SDC-SDF) radix-2 pipelined fast Fourier transform architecture, which includes log N - 1 SDC stages, and 1 SDF stage. The SDC processing engine is proposed to achieve 100% hardware resource utilization by sharing the common arithmetic resource in the time-multiplexed approach, including both adders and multipliers. Thus, the required number of complex multipliers is reduced to log 2 N - 0.5, compared with log N - 1 for the other radix-2 SDC/SDF architectures. In addition, the proposed architecture requires roughly minimum number of complex adders log 2 N + 1 and complex delay memory 2N + 1.5log 2 N - 1.5


 


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  • Model: PROJ5107
  • 999 Units in Stock
  • Manufactured by: ClickMyProjects

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This product was added to our catalog on Monday 12 September, 2016.

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